SS1102C datasheet(59/129 Pages) ETC1

59 / 129 page

Direct Sequence Spread Spectrum Baseband Modem (SSTM)

PRELIMINARY V1.8

Figure 20.

PLLSW Timing (Full-Duplex Mode)

12.16. Programming the SSTM

In the following, a brief discussion on programming the SSTM for the various modes of

operation is presented. First, the loading of the PN sequences A, B, C, and D is required

for operation in all modes.

The programming of the PLSL, CNTLR, ACC1RES, and WSL depend on several

environmental and system related factors. For example, the sizing of PLSL and CNTLR

windows involves trade-off considerations in the PLL’s dynamic performance. In

general, if smaller window size is used, the PLL will behave as if it has a smaller loop

bandwidth with higher noise filtering but at the expense of slower dynamic response. If

larger window size is used, the PLL will respond quicker dynamically but its

performance will be degraded because more noise is allowed to enter the system. Please

note that the width of the Central Zone must be smaller than or equal to the size of the

ESD window (this means that the ESD window size should NOT be set to 8, it was

included on the chip for testing purpose only).

Similarly, the width of the detection window, WSL, should be large enough to take

advantage of multipath combining but should not be so large that excessive noise is

allowed into the receiver causing receiver sensitivity degradation. In general, these

parameters can be experimentally optimized for a particular environment. Otherwise, it

is recommended that these parameters be programmed to values in the middle of the

programmable range (for example, set PLSL to 12 samples wide, CNTLR to 10 samples

wide, and WSL to 8 samples wide).

In the full-duplex or TDD mode, ACC1RES should normally be set to “0” for no ACC1

reset during each “freeze PLL” period. The only instance where ACC1RES should be

set “1” to reset ACC1 is if the frequency offset between the transmitter and receiver is

known to be very small. In this case, the performance of the PLL will be slightly

enhanced if ACC1 is reset during each “freeze PLL” period. In half-duplex operation.

ACC1RES should be set to “1” to always reset ACC1.

Tburst_clk

TXEN

PLLSW

Receive

Transmit

Receive

Not drawn to scale.

Note: G2=28xTburst_clk

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