Direct Sequence Spread Spectrum Baseband Modem (SSTM)
38
PRELIMINARY V1.8
12.3.
TDD Controller
The time-division duplex (TDD) controller implements the “ping-pong” protocol that
allows a full-duplex link to be emulated by a half-duplex radio. The TDD controller also
generates the appropriate clock and control signals to other modules of the SSTM. In
full-duplex mode, the TDD controller multiplexes and de-multiplexes the overhead bits
with the data bit-stream. The TDD controller also uses a digital phase locked loop to
maintain an equal read and write rate to the FIFOs as to avoid FIFO overflow or
underflow. In addition, the TDD controller contains logic to generate the proper
handshaking signals.
12.4.
FIFOs
The transmit and receive FIFOs are used to buffer the transmit and receive data. The
SSTM includes a 30-byte transmit FIFO and a 30-byte receive FIFO to buffer the input
and output data. The control signals for the FIFOs are generated by the TDD controller.
The FIFOs provide the internal interrupt signals for the microprocessor.
12.5.
Master Clock Generator
The master clock generator generates the various clock signals required by the modules
described above. It can be disabled in power saving mode.
12.6.
Full-Duplex Operation
Although the SSTM actually only uses a half-duplex channel for communication with
the remote device, full-duplex operation is provided by using a time-division duplex
(TDD) protocol. The TDD protocol basically configures the SSTM alternatively as a
transmitter and as a receiver. When two devices are communicating with each other,
one is programmed to be the master, while the other is programmed to be the slave. The
TDD protocol ensures that while the master is transmitting, the slave is receiving and
vice versa in a timely fashion. The end result is that as far as the user is concerned, the
communication link appears to be full-duplex. In order to achieve this, it is necessary
for the SSTM to transmit at a higher rate than the actual user data rate. Ideally, for TDD
operation, with 100% efficiency and 0% overhead, the SSTM must transmit the data at
twice the user data rate since the SSTM has only half the time to transmit the user data
(during the other half time period, the SSTM is receiving from the remote station).
Overhead such as preamble, unique word (UW), as well as other signaling information
bits result in the SSTM transmitting at 2.6 times the effective user data rate. The size of
the FIFOs on the SSTM is designed to provide sufficient buffer during both transmit
and receive operations so that underflow or overflow of the FIFOs does not occur.
When communication between two devices first commences, the microprocessors must
program one of the devices as the Master and the other device as the Slave. The master
device transmits periodic bursts as soon as the reset signal is released. The burst timing
of the Master is derived from its internal master clock oscillator and can be computed
from (EQ 1) below:
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