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External Interrupts
92
PRELIMINARY V1.8
15.3.
Interrupt Request Registers (INT0, INT1, INT2)
]
TABLE 63.
Definition of INT0
TABLE 64.
Definition of INT1
Address
D8H
Bit Addr.
DFH
DEH
DDH
DCH
DBH
DAH
D9H
D8H
BIT
7
6
5
4
3
2
1
0
NAME
IRQ2F
IRQ1F
Definition
Reserved
bit
Reserved
bit
Reserved
bit
Reserved
bit
Reserved
bit
Reserved
bit
IRQ2
Request
1:
Request
0: No
IRQ1
Request
1:
Request
0: No
Reset Value
0
0
0
0
0
0
0
0
Read/Write
by Software
R
R
R
R
R
R
R/W
R/W
Write
by Hardware
Set by
IRQ2
Event
Set by
IRQ1
Event
Address
E8H
Bit Addr.
EFH
EEH
EDH
ECH
EBH
EAH
E9H
E8H
BIT
7
6
5
4
3
2
1
0
NAME
SWINT
SNRINT
SPIINT
RXFINT
TXFINT
LOCKINT
Definition
Reserved
bit
Signaling-
Word
Interrupt
1:
Request
0: No
S/N Ratio
Interrupt
1:
Request
0: No
SPI
Interrupt
1:
Request
0: No
Reserved
bit
RXFIFO
Interrupt
1:
Request
0: No
TXFIFO
Interrupt
1:
Request
0: No
LOCK
Interrupt
1:
Request
0: No
Reset Value
0
0
0
0
0
0
0
0
Read/Write
by Software
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Write
by Hardware
Set by
SW Detect
Set by
S/N Ratio
Detect
Set by
SPI data
Ready
Set by
RXFIFO
Threshold
Set by
TXFIFO
Threshold
Set by
LOCK
Detect
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