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Direct Sequence Spread Spectrum Baseband Modem (SSTM)
48
PRELIMINARY V1.8
new data will be loaded onto the register until the interrupt it has been read and cleared
by the microprocessor. On the transmit side an interrupt pending TXSW bit is asserted
when the Signaling Word has been sent. The Signaling Word is updated or sent once
every burst. The Signaling Word may also send interrupts to the CPU in the SS1102C
(See the interrupt section for more details). The S/N data is calculated from the AGC
circuit inside the SSTM once every 128 data bits (including overhead bits).
12.12. Control Registers
One register is available for controlling the SSTM block within the SS1102C. It is the
SSTM control register. This register contains the enable and software reset for the
SSTM module. It also contains the control to enable certain outputs of the SSTM to the
SS1102 pins. Clearing the Reset bit in SSTMCR will clear the FIFO and the Reset bit
will return by the hardware to “1” after it was cleared.
TABLE 29.
Table: Definition of SSTMCR
12.13. SSTM Control Registers
A total of thirty-one registers are available for storing the various SSTM programming
parameters. They are listed below:
Address
C1H
Bit Address
BIT
765
43210
NAME
RESET
ENABLE
LOCKO
E
PLLSW
OE
RFP-
WROE
TXE-
NOE
MOD-
OUTOE
Definition
Software
Reset for
SSTM
0-reset
1-no
reset
Enable
for
SSTM
1-enable
0-disable
LOCK
output to
P4.2
1-enable
0-disable
PLLSW
output to
P4.1
1-enable
0-disable
RFPWR
output to
P4.0
1-enable
0-disable
TXEN
output to
P3.3
1-enable
0-disable
MOD-
OUT
output to
P3.4
1-enable
0-disable
Reset Value
010
00000
Read/Write
by Software
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Write
by Hardware
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