SS1102C datasheet(49/129 Pages) ETC1

49 / 129 page

Direct Sequence Spread Spectrum Baseband Modem (SSTM)

PRELIMINARY V1.8

time for receiving RXshh bytes from the channel should be more than the time required

by the MCU to read the data from the RX FIFO.

12.10. Half-duplex Operation

The half-duplex data mode is suitable for applications such as wireless LAN or pocket

radio. The SSTM does not make any assumption about the higher level protocol and

relies on these higher level protocols to provide the necessary framing, error correction,

and preamble. The SSTM will transmit and deliver the data stream without multiplexing

any protocol overhead bits, as it is the case for the full-duplex operation. Having the

serial data stream from the channel and 8-bit wide parallel bus interface to the CPU, the

data bytes should be aligned starting from the first bit of data. this alignment is

supported by the SSTM hardware. The data alignment is achieved in the half duplex

mode by the inserting the UW into the data stream as follows:

1. On the transmit side a 24 bits UW (22 bits of the UW and 2 bits “don't care”) should

be inserted in front of the first data bit by the software. The 2 bits “don’t care” are the

two MSBs of Byte0. The UW should not be loaded into the 3 UW registers of SS1105.

2. On the receive side the same 3 bytes of the UW should be loaded into the 3 UW

registers of the SS1105.

3. A receiver recognizes the UW by SS1105 hardware and loads the data into the

receive FIFO. The interrupt from the receive FIFO will be generated only after the UW

was received properly. The data will be aligned in the receive FIFO by bytes.

4. The UW should be reloaded in the receiver each time the direction of transmission is

changed (it should be done anyway because the chip will reset when the RTS_N value is

changed). Thus if a transmitter became a receiver, the UW should be loaded into the

5. All required preamble bits should be sent anyway (at least 70 of them). The “Lock”

UW is not received. It means that the “Lock” signal and “Lock” bit can be generated

before the interrupt from the RXFIFO.

6. The UW should be inserted into the data stream as follows:

Transmit side: (Byte2 MSB first) (Byte1 MSB first) (Byte0 MSB first) (Preamble

bits) ->

The transmit data and preamble should be loaded into the TX fifo in the following

order:

Preamble N byte

Byte0

Byte1

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