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Capture Timers 1/2
18
PRELIMINARY V1.8
During up-counting, the content of 16-bit counter (CT1CNTH & CT1CNTL or
CT2CNTH & CT2CNTL) will be capture into the 16-bit latch (CT1DATH &
CT1DATL or CT2DATH & CT2DATL) when an event of CPTRU1 (or CPTRU2) is
detected. One of three event (positive edge, negative edge, or any edge) can be selected
by the CT1MD[1:0] bits (or CT2MD[1:0]) in the CT1CR (or CT2CR). To use this
feature, the CPTRU1 pin (or CPTRU2 pin) should be assigned an input port by the port
control register. Using the Capture Mode, external clock period or pulse width (high
width or low width) can be measured.
Note: While in Capture mode, the CTDATH and CTDATL are still writable by S/W.
Figure 8.
Capture Timer in Capture Mode
9.5.
Capture Timer Control Registers (CT1CR/CT2CR)
Address
D1H/E1H
Bit Addr.
BIT
7
6
5
4
3
2
1
0
Fsys/12
Ffast/24
Ffast/25
Ffast/27
Ffast/210
Ffast/214
Ffast/218
CPTRU
MUX
CTCNTH:CTCNTL
16-bit up-counter
CTDATH:CTDATL
end
clear
CTEN
CTCNTLRCTFS
[7]
[6]
[5:3]
[2:0]
8-bit data bus
Edge Detector
pos/neg/both
CPTRU
ena
Catch
CT1OVUN CT1OV CT1UN
[7]
[6]
[5]
overflow
CT1SR
CTint
CT1CR
CTMD
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