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DA6021 Datasheet(PDF) 129 Page - Renesas Technology Corp |
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DA6021 Datasheet(HTML) 129 Page - Renesas Technology Corp |
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129 / 225 page ![]() DA6021 HIGHLY INTEGRATED POWER MANAGEMENT IC FOR INTEL® ATOM™ Z3000 PROCESSOR Company Confidential Data Sheet Version 3.A - Final 31-Jan-14 © 2014 Dialog Semiconductor GmbH 129 of 224 www.dialog-semiconductor.com System Voltage Monitor 14.2.6 For the system voltage comparator is meaningful to be acknowledged once the VSYS is considered valid. This can be done via simple comparator and fixed thresholds. For lower threshold the behavior must be seen together with the POR. Figure 62: VSYS Valid Input Power Detection Parameter Description Min Typ Max Unit Val VSYSREFH VSYS Rising Threshold (VSYS: L->H) 2.975 3.0 3.035 V A VSYSREFL VSYS Falling Threshold (VSYS: H->L) 2.675 2.70 2.725 V A tDEBOUNCE VSYS comparator debouncing time 90 100 110 ms A Table 95: VSYSREF Definition VBUS Power Source Detection 14.3 Following is the diagram of the VBUS voltage detection. Figure 63: USB Detection VBUS Rising (Connection Event) When the VBUS level at the comparator becomes higher than reference voltage (including rising edge hysteresis), VBUS is considered valid. If the VBUSDBEN bit is set in the VBUSDETCTRL register, VBUS must be sensed as valid for the full 100ms de-bounce time before the SVBUSDET bit in the SPWRSRCIRQ register is set, indicating charger connection. If VBUSDBEN is cleared, SVBUSDET is set immediately upon VBUS becoming valid. VSYS analog external digital 2.7V – 3.0V sync Deb/ 100ms VBUS analog external digital 0.89V – 0.98V sync Deb/ 100ms EN ST IRQ MSK IRQ_LVL1 |
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