DA6021 datasheet(130/225 Pages) RENESAS

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DA6021

HIGHLY INTEGRATED POWER MANAGEMENT IC FOR

INTEL® ATOM™ Z3000 PROCESSOR

Company Confidential

Data Sheet

Version 3.A - Final

31-Jan-14

130 of 224

www.dialog-semiconductor.com

VBUS Falling (Disconnection Event)

When the VBUS level at the comparator becomes lower than reference voltage (including falling edge

hysteresis), VBUS is considered invalid. If the VBUSDBEN bit is set in the VBUSDETCTRL register, VBUS must

be sensed as invalid for the full 100ms de-bounce time before the SVBUSDET bit in the SPWRSRCIRQ register

is cleared, indicating charger disconnection. If VBUSDBEN is cleared, SVBUSDET is cleared immediately upon

VBUS becoming invalid.

On any change in the SVBUSDET bit in the SPWRSRCIRQ register (set or clear), the corresponding interrupt

flag, VBUSDET, is set in the PWRSRCIRQ 2

nd-level interrupt register. This automatically sets the PWRSRC

interrupt flag in the IRQLVL1 interrupt register, and alerts the SOC. The SOC is expected to query the

SVBUSDET bit in SPWRSRCIRQ to determine if the event was a connection or disconnection.

Analog electrical parameters:

Parameter

Symbol

Condition

Min

Typ

Max

unit

Val

Static parameters

Rising Threshold

895

940

990

Falling Threshold

810

860

900

Hysteresis

D,E

Dynamic parameters

Rising Delay

D,E

Falling Delay

D,E

Table 96: VBUS Detection, Analog Electrical Parameters

VDCIN Power Source Detection Comparators

14.4

The VDCIN_SENSE detection will be done in a similar fashion as for the VBUS.

Figure 64: DCIN Detection

The same sequence of operation as in the case of the VBUS will be followed to decide on the booting. After

detecting the DCIN an IRQ on removal / Insertion event will be generated.

VDCIN Rising (Connection Event)

When the VDCIN level at the comparator becomes higher than the reference voltage (including rising edge

hysteresis), VDCIN is considered valid. If the VDCINDBEN bit is set in the VDCINDETCTRL register, VDCIN

must be sensed as valid for the full 100ms de-bounce time before the SDCINDET bit in the SPWRSRCIRQ

VDCIN becoming valid.

analog

external

0.89V

– 0.98V

sync

Deb/

100ms

IRQ

MSK

IRQ_LVL1

VDCIN

digital

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