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TMS320F Datasheet(PDF) 321 Page - Texas Instruments

Part # TMS320F
Description  CPU and Instruction Set
PDF  389 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320F Datasheet(HTML) 321 Page - Texas Instruments

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Instruction Set Comparison Table
A-25
TMS320C1x/C2x/C20x/C5x Instruction Set Comparison
Syntax
Description
5x
2xx
2x
1x
OR
dma
OR
{
ind} [, next ARP]
OR
#
lk [, shift]
√
√
√
√
√
√
√
√
√
√
OR With Accumulator
TMS320C1x and TMS320C2x devices: OR the 16
LSBs of the accumulator with the contents of the
addressed data-memory location. The 16 MSBs of the
accumulator are ORed with 0s.
TMS320C20x and TMS320C5x devices: OR the 16
LSBs of the accumulator or a 16-bit immediate value
with the contents of the addressed data-memory
location. If a shift is specified, left-shift before ORing.
Low-order bits below and high-order bits above the
shifted value are treated as 0s.
ORB
√
OR ACCB With Accumulator
OR the contents of the ACCB with the contents of the
accumulator.
ORB
places
the
result
in
the
accumulator.
ORK #
lk [, shift]
√
√
√
OR Immediate With Accumulator with Shift
OR a 16-bit immediate value with the contents of the
accumulator. If a shift is specified, left-shift the
constant before ORing. Low-order bits below and
high-order bits above the shifted value are treated as
0s.
OUT
dma, PA
OUT {
ind}, PA [, next ARP]
√
√
√
√
√
√
√
√
Output Data to Port
Write a 16-bit value from a data-memory location to the
specified I/O port.
TMS320C1x devices: The first cycle of this instruction
places
the
port
address
onto
address
lines
A2/PA2–A0/PA0. During the same cycle, WE goes low
and the data word is placed on the data bus D15–D0.
TMS320C2x,
TMS320C20x,
and
TMS320C5x
devices: The IS line goes low to indicate an I/O access;
the STRB, R/W, and READY timings are the same as
for an external data-memory write.
PAC
√
√
√
√
Load Accumulator With P Register
Load the contents of the P register into the
accumulator.
TMS320C2x,
TMS320C20x,
and
TMS320C5x
devices: Before the load, shift the P register as
specified by the PM status bits.



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