TMS320F datasheet(353/389 Pages) TI

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Emulation Design Considerations

C-18

C.8.2 Emulation Timing Calculations for a Scan Path Linker (SPL)

The examples in this section help you to calculate the key emulation timings

in the SPL secondary scan path of your system. For actual target timing pa-

rameters, see the appropriate device data sheet for your target device.

The examples use the following assumptions:

tsu(TTMS)

Setup time, target TMS/TDI to TCK high

10 ns

td(TTDO)

Delay time, target TDO from TCK low

15 ns

td(bufmax)

Delay time, target buffer, maximum

10 ns

td(bufmin)

Delay time, target buffer, minimum

1 ns

t(bufskew)

Skew time, target buffer, between two

devices in the same package:

[td(bufmax) – td(bufmin)] × 0.15

1.35 ns

t(TCKfactor)

Duty cycle, TCK assume a 40/60% clock

0.4

(40%)

Also, the examples use the following values from the SPL data sheet:

td(DTMSmax)

Delay time, SPL DTMS/DTDO from TCK

low, maximum

31 ns

tsu(DTDLmin)

Setup time, DTDI to SPL TCK high,

minimum

7 ns

td(DTCKHmin) Delay time, SPL DTCK from TCK high,

minimum

2 ns

td(DTCKLmax) Delay time, SPL DTCK from TCK low,

maximum

16 ns

There are two key timing paths to consider in the emulation design:

- The TCK-to-DTMS/DTDO path, called tpd(TCK-DTMS)

- The TCK-to-DTDI path, called tpd(TCK-DTDI)

TMS320F Datasheet(PDF) 353 Page - Texas Instruments

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