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PM7346 Datasheet(PDF) 245 Page - PMC-Sierra, Inc |
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PM7346 Datasheet(HTML) 245 Page - PMC-Sierra, Inc |
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245 / 419 page ![]() PM7346 S/UNI-QJET DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3 PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 224 Register 063H, 163H, 263H, 363H: RXCP-50 Interrupt Enables and Counter Status Bit Type Function Default Bit 7 R XFERI X Bit 6 R OVR X Bit 5 Unused X Bit 4 R/W XFERE 0 Bit 3 R/W OOCDE 0 Bit 2 R/W HCSE 0 Bit 1 R/W FOVRE 0 Bit 0 R/W LCDE 0 LCDE: The LCDE bit enables the generation of an interrupt due to a change in the LCD state. When LCDE is set to logic 1, the interrupt is enabled. FOVRE: The FOVRE bit enables the generation of an interrupt due to a FIFO overrun error condition. When FOVRE is set to logic 1, the interrupt is enabled. HCSE: The HCSE bit enables the generation of an interrupt due to the detection of a corrected or an uncorrected HCS error. When HCSE is set to logic 1, the interrupt is enabled. OOCDE: The OOCDE bit enables the generation of an interrupt due to a change in cell delineation state. When OOCDE is set to logic 1, the interrupt is enabled. XFERE: The XFERE bit enables the generation of an interrupt when an accumulation interval is completed and new values are stored in the RXCP-50 Count registers. When XFERE is set to logic 1, the interrupt is enabled. |
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