PM7346 datasheet(243/419 Pages) PMC

243 / 419 page

PM7346 S/UNI-QJET

DATASHEET

PMC-960835

ISSUE 6

SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 222

Bit

Type

Function

Default

Bit 7

R/W

RXPTYP

Bit 6

Unused

Bit 5

R/W

RCAINV

Bit 4

R/W

RCALEVEL0

Bit 3

Unused

Bit 2

Unused

Bit 1

Unused

Bit 0

R/W

FIFORST

FIFORST:

The FIFORST bit is used to reset the four-cell receive FIFO. When FIFORST

is set to logic 0, the FIFO operates normally. When FIFORST is set to logic 1,

the FIFO is immediately emptied and further writes into the FIFO are ignored

(no incoming ATM cells will be stored in the FIFO). The FIFO remains empty

and continues to ignore writes until a logic 0 is written to FIFORST.

See section 12.8 on resetting the receive and transmit FIFOs.

RCALEVEL0:

The RCALEVEL0 register bit selects the behavior of RCA and DRCA[x] when

they de-assert (transition to logic 0 if RCAINV is logic 0, or transition to logic 1

if RCAINV is logic 1) as the receive FIFO empties.

When RCALEVEL0 is set to logic 1, DRCA[x] and RCA indicates that the

receive FIFO is empty. RCA (and DRCA[x]), if polled, will de-assert on the

rising RFCLK edge after Payload byte 48 (ATM8=1) or Payload byte 24

(ATM8=0) is output.

When RCALEVEL0 is set to logic 0, DRCA[x] and RCA, if polled, indicates

that the receive FIFO is near empty. DRCA[x] and RCA, if polled, will de-

assert on the rising RFCLK edge after Payload byte 43 (ATM8=1) or Payload

byte 19 (ATM8=0) is output.

PM7346 Datasheet(PDF) 243 Page - PMC-Sierra, Inc

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