PM7346 datasheet(263/419 Pages) PMC

263 / 419 page

PM7346 S/UNI-QJET

DATASHEET

PMC-960835

ISSUE 6

SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 242

HCSB:

The active low HCSB bit enables the internal generation and insertion of the

HCS octet into the transmit cell stream. When HCSB is logic zero, the HCS is

generated and inserted internally. When the HCSB and DS27_53 register

bits are logic one, the HCS octet read from the transmit FIFO is inserted

transparently into the transmit cell stream, but the TXCP-50 will still generate

and insert the HCS octet for idle cells. If HCSB is logic one and the 26 word

data structure is selected (DS27_53 is logic 0), then no HCS octet is inserted

in the transmit data stream.

HCSDQDB:

The HCSDQDB bit controls the cell header octets included in the HCS

calculation. When a logic 1 is written to HCSDQDB, header octets, 2, 3, and

4 are included in the HCS calculation as required by IEEE-802.6 DQDB

specification. When a logic 0 is written to HCSDQDB, all four header octets

are included in the HCS calculation as required by the ATM Forum UNI

specification and ITU-T Recommendation I.432.

HSCR:

The Header Scramble enable bit, HSCR, enables scrambling of the ATM five

octet header along with the payload. When set to logic one, the ATM header

and payload are both scrambled. When set to logic zero, the header is left

unscrambled and payload scrambling is determined by the DSCR bit.

TCALEVEL0:

The active high TCA (and DTCA[x]) level 0 bit, TCALEVEL0 determines what

output TCA (and DTCA[x]) indicates when it de-asserts (transitions to logic 0

if TCAINV is logic 0, or transitions to logic 1 if TCAINV is logic 1).

When TCALEVEL0 is set to logic 1, TCA (and DTCA[x]) indicates that the

transmit FIFO is full and can accept no more writes. DTCA[x] and TCA, if

polled, will de-assert on the rising TFCLK edge when Payload byte 47

(ATM8=1) or Payload word 23 (ATM8=0) is sampled.

When TCALEVEL0 is set to logic zero, TCA (and DTCA[x]) indicates that the

transmit FIFO is near full. DTCA[x] and TCA, if polled, will de-assert on the

rising TFCLK edge when Payload byte 43 (ATM8=1) or Payload word 19

(ATM8=0) is sampled.

TPTYP:

The TPTYP bit selects even or odd parity for input TPRTY. When set to logic

one, input TPRTY is the even parity bit for the TDAT input bus. When set to

PM7346 Datasheet(PDF) 263 Page - PMC-Sierra, Inc

PM7346 Datasheet(HTML) 263 Page - PMC-Sierra, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL