PM7346 datasheet(154/419 Pages) PMC

154 / 419 page

PM7346 S/UNI-QJET

DATASHEET

PMC-960835

ISSUE 6

SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 133

Bit

Type

Function

Default

Bit 7

EXZS[15]

Bit 6

EXZS[14]

Bit 5

EXZS[13]

Bit 4

EXZS[12]

Bit 3

EXZS[11]

Bit 2

EXZS[10]

Bit 1

EXZS[9]

Bit 0

EXZS[8]

EXZS[15:0]:

In DS3 mode, EXZS[15:0] represents the number of summed Excessive

Zeros (EXZS) that occurred during the previous accumulation interval. One

or more excessive zeros occurrences within an 85 bit DS3 information block

is counted as one summed excessive zero. Excessive zeros are accumulated

by this register only when the EXZSO and EXZDET are logic 1 in the DS3

FRMR Additional Configuration Register. This register accumulates summed

line code violations when the EXZSO is logic 0. The count of summed line

code violations is defined as the number of DS3 information blocks (85 bits)

that contain one or more line code violations since the last time the summed

LCV counter was polled.

The counter (and all other counters in the PMON) is polled by writing to any

of the PMON register addresses (x14H to x1FH) or to the S/UNI-QJET

Identification, Master Reset, and Global Monitor Update register (006H).

Such a write transfers the internally accumulated count to the EXZS Event

Count Registers and simultaneously resets the internal counter to begin a

new cycle of error accumulation. This transfer and reset is carried out in a

manner that coincident events are not lost. The transfer takes 255 RCLK[x]

cycles to complete in DS3 mode and a maximum of 500 RCLK[x] cycles to

complete in G.832 E3 mode.

PM7346 Datasheet(PDF) 154 Page - PMC-Sierra, Inc

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