TMPR3916 datasheet(139/225 Pages) TOSHIBA

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Chapter 7 CAN Module (TXCAN)

Preliminary

7-18

This leads to the following restrictions:

Restrictions for TSEG2

BRP

TQ Length

(TXCAN clock cycles)

IPT Length

(TXCAN clock cycles)

TSEG2 Minimum Length

(in TQ)

BRP+1

Restrictions for TSEG1

The length of TSEG1 should be equal or greater than the length of TSEG2:

TSEG1

≥ TSEG2

Restrictions for SJW

The maximum length of the synchronization jump width is equal to the length of TSEG2:

SJW

≥ TSEG2

Restrictions for SAM

The three-time sampling is not allowed for BRP<4. For BRP<4 always a one-time sampling will

be performed regardless of the value of SAM.

Example:

A transmission rate of 1 MBit/s will be adjusted, i.e. a bit has a length of 1 µs. The clock

frequency fOSC is 10 MHz. The baud rate prescaler is set to “0”. That means a bit for this data

transmission rate has to be programmed with a length of 10*TQ. According to the above formula,

the values to be set are always by one smaller than the calculated values.

E.g. BRP = 1 (BRP_reg = 0);

TSEG1 = 5 (TSEG1_reg = 4), TSEG2 = 4 (TSEG2_reg = 3).

With this setting a threefold sampling of the bus is not possible (BRP<4), thus SAM = 0 should

be set. SJW is not allowed to be greater than TSEG2, so the maximum value could be set to 4 units

(SJW = 3).

7.2.8

Time Stamp Feature

There is a free-running 16-bit timer implemented in the module to get an indication of the time of

reception or transmission of messages. The content of the timer is written into the time stamp register of

the corresponding mailbox (TSV) when a received message has been stored or a message has been

transmitted.

The counter is driven from the bit clock of the CAN bus line. When the TXCAN is in configuration

mode or in sleep mode, the timer will be stopped. After power-up reset the free running counter can be

cleared by writing a value to the time stamp counter prescaler. The counter can be written and read by

the MCU in configuration mode and in normal operation mode.

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