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TMPR3916 Datasheet(PDF) 142 Page - Toshiba Semiconductor

Part # TMPR3916
Description  32-Bit TX System RISC TX39 Family TMPR3916
PDF  225 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR3916 Datasheet(HTML) 142 Page - Toshiba Semiconductor

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Chapter 7 CAN Module (TXCAN)
Preliminary
7-21
Bit
Name
Function
Reset
Value
Mode
2
BO
Bus Off status
1 = There is an abnormal rate of occurrences of errors on the CAN
bus. This condition occurs when the transmit error counter TEC
has reached the limit of 256. During “bus off”, no messages can
be received or transmitted. The CAN module will go to “bus on”
automatically after the “bus off recovery sequence”. After
entering “bus off”, the error counters are undefined.
0 = Normal operation
0
R
1
EP
Error Passive status
1 = The CAN module is in the error passive mode.
0 = The CAN module is in the error active mode.
0
R
0
EW
Warning status
1 = At least one of the error counters has reached the warning level
of 97.
0 = Both values of the error counters are less than 97.
0
R
CAN Error Counter Register (CEC)
Bit
15
8
7
0
Name
TEC
REC
Bit
Name
Function
Reset
Value
Mode
15:8
TEC
Transmit error counter
0R
7:0
REC
Receive error counter
0R
The CAN module contains two error counters: receive error counter (REC) and transmit error counter
(TEC). The values of both counters can be read via the MCU interface. These counters are incremented
or decremented according to the CAN specification version 2.0B. A write access to the error counters is
only possible in the test error mode (TSTERR bit in MCR is set). In this mode both the TEC and REC
counters take over the value written to the lower byte of the register.
The receive error counter is not increased after exceeding the error passive limit (128). After the
correct reception of a message, the counter is set to a value between 119 and 127 (see CAN
specification). After reaching the “bus off” status, the error counters are undefined.
If the status “bus off” is reached, the receive error counter is incremented after 11 consecutive
recessive bits on the bus. These 11 bits correspond to the gap between two telegrams on the bus. If the
counter reaches the count 128, the module changes automatically to the status error active. All internal
flags are reset and the error counters are deleted. The configuration registers keep the programmed
values. The values of the error counters are undefined during “bus off” status.
When TXCAN enters configuration mode (see paragraph “7.4.1 Configuration Mode”) the error
counters will be cleared.



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