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TMPR3916 Datasheet(PDF) 144 Page - Toshiba Semiconductor

Part # TMPR3916
Description  32-Bit TX System RISC TX39 Family TMPR3916
PDF  225 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR3916 Datasheet(HTML) 144 Page - Toshiba Semiconductor

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Chapter 7 CAN Module (TXCAN)
Preliminary
7-23
Bit
Name
Function
Reset
Value
Mode
3
TSOIF
Time Stamp Counter Overflow Interrupt Flag
1 = There was at least one overflow of the time stamp counter since
this bit has been cleared.
0 = There was no overflow of the time stamp counter since this bit
has been cleared.
0
R/C
2
BOIF
Bus Off Interrupt Flag
1 = The CAN has entered the bus off mode.
0 = The CAN module is still in bus on mode.
0
R/C
1
EPIF
Error Passive Interrupt Flag
1 = The CAN module has entered the error passive mode.
0 = The CAN module is still in error active mode.
0
R/C
0
WLIF
Warning Level Interrupt Flag
1 = At least one of the error counters has reached the warning level.
0 = None of the error counters has reached the warning level.
0
R/C
Note:
All interrupt flags in GIF are independent of the interrupt mask bits. The interrupt flags in
GIF can be cleared by writing a “1” to the corresponding bit position. Writing a “0” has no
effect.
Global Interrupt Mask Register (GIM)
Bit
15
8
76543210
Name
RFPF
WUIF
RMLIF TRMABF TSOIF
BOIF
EPIF
WLIF
The attachment of bits in GIM to the interrupt conditions is equal to that in GIF. Each interrupt flag bit in
GIF is masked by the corresponding mask bit in GIM. After power-up, all bits are cleared.
7.3.1
Mailbox Interrupts
There are two separate interrupt output lines for the mailboxes. One interrupt output for mailboxes,
which are configured as transmit and one for mailboxes which are configured as receive.
There are two interrupt flag registers and one interrupt mask register. One interrupt flag register is for
receive mailboxes and one for transmit mailboxes. The interrupt mask register is used for transmit and
receive mailboxes.
Mailbox Interrupt Mask Register (MBIM)
The settings in MBIM determine, for which mailbox the interrupt generation is enabled or disabled.
If a bit in MBIM is “0”, the interrupt generation for the corresponding mailbox is disabled and if it is
“1”, the interrupt generation is enabled. Reset value of MBIM is 0.
Bit
15
0
Name
MBIM



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