TMPR3916 datasheet(140/225 Pages) TOSHIBA

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Chapter 7 CAN Module (TXCAN)

Preliminary

7-19

Time Stamp Counter Register

Bit

Name

TSC

Overflow of the counter can be detected by the time stamp counter overflow interrupt flag of the

global interrupt flag register GIF and the status flag TSO in GSR. Both flags can be cleared by writing a

“1” to the corresponding bit location in GIF.

There is a 4-bit prescaler for the time stamp counter. After power-up the time stamp counter is driven

directly from the bit clock (TSP = 0). The period TTSC for the time stamp counter will be calculated with

the following formula:

)

TSP

(

BIT

TSC

∗

Time Stamp Counter Prescaler Register

Bit

43210

Name



TSP

To be sure, that the value of the counter will not change during the write cycle to the mailbox RAM,

there is a hold register implemented. The value of the counter will be copied to this register if a message

has been received or transmitted successfully. The reception is successful for the receiver, if there is no

error until the last but one bit of End-of-frame. The transmission is successful for the transmitter, if

there is no error until the last bit of End-of-frame. (Refer to the CAN specification 2.0B)

The following figure shows the structure of the time stamp counter:

Prescaler Register (4 bit)

MCU read/write

Prescaler (4 bit)

Free running

Time Stamp Counter

(16 bit)

Time Stamp Hold Register

(16 bit)

MCU read/write

Transmission/Reception

successful

CAN bus bit clock

Count-up clock

Hardware/Software reset

Entering sleep mode

Entering configuration mode

Write to prescaler

clear

load

clear

Hardware/Software reset

clear

Re-load value

Mailbox RAM

re-load

Entering sleep mode

Entering configuration mode

Write to prescaler

Figure 7.2.5 Time Stamp Counter

TMPR3916 Datasheet(PDF) 140 Page - Toshiba Semiconductor

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