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7630 Datasheet(PDF) 215 Page - Renesas Technology Corp |
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7630 Datasheet(HTML) 215 Page - Renesas Technology Corp |
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215 / 238 page ![]() 7630 Group User’s Manual 3-44 $33(1',; 3.5 List of registers Fig. 3.5.45 Structure of CAN acceptance mask register 4 (CAM4) Fig. 3.5.46 Structure of CAN receive control register (CREC) CAN acceptance mask register 4 b7 b6 b5 b4 b3 b2 b1 b0 CAN acceptance mask register 4 (CAM4) [Address: 003C16] B Name Function At reset R W1 Note 1: Writing to this register is enabled in configuration mode only (refer to section 2.4.4). 0 These bits must be set to "0". ? O O 1 ? O O 2 Extended identifier mask bit 0 ? O O 3 Extended identifier mask bit 1 ? O O 4 Extended identifier mask bit 2 ? O O 0: Mask identifier bit (don’t care) 5 Extended identifier mask bit 3 1: Compare identifier bit ? O O These bits mask the corresponding bits of the acceptance code register 4, Figure 3.5.40 from the acceptance filtering. 6 Extended identifier mask bit 4 ? O O 7 Extended identifier mask bit 5 ? O O CAN receive control register b7 b6 b5 b4 b3 b2 b1 b0 CAN receive control register (CREC) [Address: 003D16] B Name Function1 Note 1: R0/R1 denote read access, W0/W1 denote write access. At reset R W 0 Receive buffer control bit R0: Receive buffer empty (undefined) 0 O O R1: Receive buffer full W0: Release (clear) receive buffer W1: No operation 1 Receive status bit 0: CAN module idle or transmitting 0 O X 1: CAN module receiving 2 Reserved When these bits are read out, the values are "0". Don’t write to "1". 0 O X 3 0 O X 4 0 O X 5 0 O X 6 Auto-receive disable bit2 0: Auto-receive enabled 0 O O 1: Auto-receive disabled 7 Reserved When these bits are read out, the values are "0". Don’t write to "1" 0 O X Note 2: Suppresses reception of self-initiated/transmitted frames; for details see section 2.4.8, (5). |
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