TRF2443IPFPR datasheet(31/72 Pages) TI

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SPI REGISTERS

“End of Write Cycle”

pulse

1stWrite

clock

pulse

tsu1

t(CLK)

32nd

Write

clock

pulse

CLOCK

DATA

t(CL)

t (CH)

LATCH

ENABLE

DB30

DB29

DB2

Address Bit2

DB1

Address Bit1

DB0 (LSB)

Address Bit0

DB3

Address Bit3

DB31(MSB)

TRF2443 Addressing Scheme

TRF2443

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The TRF2443 features a three-wire serial programming interface (SPI) that controls an internal 32-bit shift

and the latch enable (LESPI). The TRF2443 has an additional pin (RDBKSPI) for readback functionality. This pin

is a digital pin and can be used to read back values of different internal registers.

The DATA (DB0–DB31) is loaded LSB-first and is read on the rising edge of the CLOCK. The latch enable is

asynchronous to the CLOCK, and at its rising edge the data in the shift register is loaded onto the selected

internal register. The 5 LSBs of the data field are the address bits to select the available internal registers (see

Figure 99).

The SPI can operate reliably at clock speeds up to 20 MHz (clock period <50 ns). In theory, two 32-bit registers

could be programmed within 3.3

µs (64 clock cycles at 50 ns per clock cycle plus setup times). However, the

user must exercise care when writing consecutive registers to ensure that subsequent register writes do not

disrupt a previously requested operation such as a calibration. Calibration times are functions of the external

reference frequency used as well as internally programmable clock dividers set by the user. The application

section of this data sheet describes how to determine these calibration times. The user should allow for such

calibration times when writing registers to the serial interface that contain settings related to the calibration or

settings related to the circuits which are being calibrated.

Figure 99. SPI Timing Diagram

Table 1. SPI Timing – Writing Phase

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

Hold time, data to clock

tSU1

Setup time, data to clock

t(CL)

Clock low duration

t(CH)

Clock high duration

tSU2

Setup time, clock to enable

Enable Time

t(CLK)

Clock period

tSU3

Setup time, latch to data

The TRF2443 has a separate set of register banks for the EEPROM (SPI-0), TX PLL (SPI-1), RX PLL (SPI-2),

and TX/RX functionality (SPI-3). Each of the register banks has unique address bits to identify it, and within each

Each register is 32 bits long; the bits can be described by B<31,0>. The 5 LSBs of each register, (B<4,0>), are

the address bits, with B<4,3> corresponding to the address of the register bank and B<2,0> corresponding to the

address of the individual register within each bank (see Table 2).

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