TRF2443IPFPR datasheet(64/72 Pages) TI

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TX LO Leakage Calibration

RX IMAGE REJECTION

2Acos

Rejection(dB) = 10log

2Acos

DC-OFFSET CALIBRATION

TRF2443

SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com

Because the corner frequency is dependent on the on-chip capacitance, it is possible to observe variations from

unit to unit in the SPI code that yields a fixed corner frequency. Variations in capacitance from unit to unit result

in a unique 1/BW curve for each unit. If the same DUT is to be used at multiple corner frequencies, the user

should calibrate the DUT as described above to determine, at a minimum, 2 points on the 1/BW curve. From

these calibrated points, any other corner frequency can be extrapolated using linear regression.

The TRF2443 internal feedback path can be used to set up an automatic calibration of the TX LO leakage

according the following potential procedure:

1. Enable loopback switch with minimum insertion loss.

EN_LB_ATT = 0 (SPI-3, register 1, B<19>)

EN_LB = 1 (SPI-3, register 1, B<18>)

2. Set RXLO = 330 MHz (RXVCO to 2640 MHz and RX divider to 8)

RXRDIV<13,0> = <00 0000 0000 0001> (SPI-2, register 1, B<18,5>) [R = 1]

RX_NINT<15,0> = <0000 0000 1000 0100> (SPI-2, register 2, B<20,5>) [N = 132]

RXDIV_SEL = 1 (SPI-2, register 2, B<26>) [LO divider set to 8]

3. Set RX baseband in filter bypass mode and gain = 22 dB

RXBB_GAIN<4,0> = <01101> (SPI-3, register 2, B<15,11>) [gain = 22 dB]

RXBB_FLT_BYP = 1 (SPI-3, register 2, B<23>) [bypass filter]

4. Program TX LO in normal mode (TXLO = 340 MHz).

TXRDIV<13,0> = <00 0000 0000 0001> (SPI-1, register 1, B<18,5>) [R = 1]

TX_NINT<15,0> = <0000 0000 0100 0100> (SPI-1, register 2, B<20,5>) [N = 68]

TXDIV_SEL = 1 (SPI-1, register 2, B<26>) [LO divider set to 8]

5. Measure power level at RXBB output at 10 MHz = P1.

6. Change TX input dc offset until minimum P1 is achieved.

The TRF2443 TX baseband inputs can be ac- or dc-coupled to the external digital-to-analog converter (DAC). In

case of direct coupling, the DAC must provide the appropriate dc offset of step 6 to null the LO leakage. If an

ac-coupled approach is selected, then the internal bias must be enabled by setting EN_TXCM = 1 (SPI-3,

programmed via the SPI. TXBBI<5,0> (SPI-3, register 3, B<30,25>) and TXBBQ<5,0> (SPI-3, register 3,

B<24,19>) control the internal DAC settings.

TXBBI<5,0> = TXBBQ<5,0> = <10 0000> corresponds to midrange, that is, no offset applied.

The TRF2443 has been designed to provide optimal image rejection. Using symmetry in the design of the I and

Q paths of the receiver ensures that mismatch between the I and Q paths is minimized. Image rejection is a

function of the amplitude (A) mismatch and the phase error (

Φ) from 90 degrees of the I and Q RX baseband

signals. Image rejection is calculated in the following manner:

The TRF2443 provides an automatic calibration procedure for adjusting the dc offset in the receiver and XPIC

baseband I/Q paths. The internal calibration requires a clock in order to function. This clock is derived internally

from the reference clock with a frequency divider, whose divider ratio is programmable. DCOFF_CLK<2,0>

(SPI-3, register 5, B<16,14>) and XDCOFF_CLK<2,0> (SPI-3, register 5, B<29,27>) set the division ratio for the

dc-offset correction-loop clock for the receiver and XPIC chains, respectively.

The

output

full-scale

range

the

internal

dc-offset-correction

DAC

programmable

using

bits

DCOFF_BIAS<1,0> (SPI-3, register 5, B<13,12>) for the receiver chain and XPICDCOFF_BIAS<1,0> (SPI-3,

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TRF2443IPFPR Datasheet(PDF) 64 Page - Texas Instruments

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