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TRF2443IPFPR Datasheet(PDF) 48 Page - Texas Instruments |
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TRF2443IPFPR Datasheet(HTML) 48 Page - Texas Instruments |
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48 / 72 page  TRF2443 SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com REGISTER NAME POWER-ON SUGGESTED DESCRIPTION 5 VALUE VALUE Bit31 PWD_XPICDCOFF 0 0 Power down XPIC dc-offset loop (1 = disable) EN_BB_AUTOCAL (bit5): When 1, the RX baseband dc-offset automatic calibration starts. At the end of the calibration, the bit is reset to 0. DCOFF_BIAS<2,0>: These bits control the maximum output dc voltage of the dc-offset correction DAC used in the RX chain. DCOFF_CLK<2,0>: It sets the frequency-divider ratio that creates the RX dc-offset correction-loop clock from the clock divider. EN_BB_CAL (bit17): When 1, the RX baseband dc-offset loop is enabled. EN_XPIC_AUTOCAL (bit18): When 1, the XPIC baseband dc-offset automatic calibration starts. At the end of the calibration, the bit is reset to 0. XPICDCOFF_BIAS<2,0>: These bits control the maximum output dc voltage of the dc-offset correction DAC used in the XPIC chain. XDCOFF_CLK<2,0>: It sets the frequency-divider ratio that creates the XPIC dc-offset correction-loop clock from the clock divider. SPI3 Register 6 IFVGA2 gain- Register address SPI address IFVGA3 gain-range control IFVGA3 min. gain range control Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14 Bit15 IFVGA2 gain-range IFVGA2 min. gain IFVGA1 gain-range control IFVGA1 min. gain control Bit16 Bit17 Bit18 Bit19 Bit20 Bit21 Bit22 Bit23 Bit24 Bit25 Bit26 Bit27 Bit28 Bit29 Bit30 Bit31 REGISTER POWER-ON SUGGESTED NAME DESCRIPTION 6 VALUE VALUE Bit0 ADDR_0 0 0 Register address bits Bit1 ADDR_1 1 1 Bit2 ADDR_2 1 1 Bit3 ADDR_3 1 1 SPI address bits Bit4 ADDR_4 1 1 Bit5 IFVGA3_RANGE_0 0 0 IFVGA3 gain-range control Bit6 IFVGA3_RANGE_1 0 1 Bit7 IFVGA3_RANGE_2 1 0 Bit8 IFVGA3_RANGE_3 1 1 Bit9 IFVGA3_RANGE_4 1 0 Bit10 IFVGA3_ MINGAIN_0 0 0 IFVGA3 minimum-gain control Bit11 IFVGA3_MINGAIN_1 1 1 Bit12 IFVGA3_MINGAIN_2 0 0 Bit13 IFVGA3_MINGAIN_3 0 0 Bit14 IFVGA2_RANGE_0 0 1 IFVGA2 gain-range control Bit15 IFVGA2_RANGE_1 0 0 Bit16 IFVGA2_RANGE_2 1 0 Bit17 IFVGA2_RANGE_3 1 1 Bit18 IFVGA2_RANGE_4 1 0 Bit19 IFVGA2_ MINGAIN_0 0 0 IFVGA2 minimum-gain control Bit20 IFVGA2_MINGAIN_1 1 1 Bit21 IFVGA2_MINGAIN_2 0 0 Bit22 IFVGA2_MINGAIN_3 0 0 48 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TRF2443 |
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