TRF2443IPFPR datasheet(54/72 Pages) TI

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TRF2443 DESCRIPTION

RECEIVER DESCRIPTION

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RXVGA

LNA

FromSPI

fromRXPLL

AGC

CNTL

IFVGA1

IFVGA2

IFVGA3

FromSPI

BB AMP/FLT

IFSAW

RX_IN

IF_OUT

IF_IN

RX_BBI

RX _BBQ

RX_AGC

LNA

VGA

Demodulator

TRF2443

SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com

Figure 101. Receiver Chain Block Diagram

The TRF2443 features a highly linear low-noise receiver chain with over 60 dB of analog-controlled gain range

and more than 40 dB of gain range programmable via the serial programming interface (SPI) in 1-dB steps.

Moreover, the TRF2443 gives the flexibility to add an external IF filter to further remove unwanted signals. Such

an external filter can be bypassed using an internal path that can be enabled via SPI.

The first block of the receiver chain is a low-noise, highly linear IF amplifier (LNA). Its input is differential and

internally matched to 50

Ω. To drive the TRF2443 RX input via a single0-ended source, a 1:1 balun is required at

the LNA input (see Application Schematic section). The TRF2443 LNA attenuation is programmable via the serial

programming interface (SPI) from 0 dB to –19 dB, corresponding to an LNA gain of 17 dB to –2 dB (1-dB steps).

LNA_ATT<4,0> in SPI-3, register 2, B<9,5> are the LNA attenuation controlling bits. To program the amplifier to

the maximum gain, set the attenuation bits to 0 (LNA_ATT<4,0> = <0 0000>); whereas minimum gain

corresponds to LNA_ATT<4,0> = <1 0011>.

The LNA is followed by three analog-controlled VGAs that provide more than 60 dB of gain range. The IFVGA1

output and IFVGA2 input can be connected externally (pins IFOUT and IFIN) through an external IF filter. The

IFVGA1 output buffer requires two pullup inductors to be connected from the IFOUTP/N pins to Vcc (see

Application Schematic section). The IFVGA2 input (pins IFINN/P) is high-impedance. A 50-

Ω external resistor is

required across the IFINN and IFINP pins to provide a matching load to the IF filter output. An internal switch

gives the flexibility to bypass the external filter. The internal bypass switch is controlled via the serial

programming interface through bit EN_SAW (SPI-3, register 2, B<10>). By programming EN_SAW to 1, the

external path is selected, whereas a 0 engages the internal bypass switch.

The VGA gain is controlled by the dc voltage applied to the RXAGC pin. By varying the input dc voltage from 0 V

to 2 V, the VGA total gain goes from minimum to maximum. The gain control is linear in dB, with a typical slope

around 51 dB/V. The RXAGC input provides a high input impedance, equivalent to a 100-k

Ω resistance in series

with a 4-pF capacitance.

The IFVGA3 drives the demodulator, which downconverts the IF input signal directly to baseband in phase and

quadrature. The demodulator block includes the local oscillator in-phase and quadrature-generation circuitry,

followed by the LO buffer. The LO chain also includes a frequency divider that can be programmed to divide by 8

or 16. The frequency divider generates the RX LO from the RX VCO. By selecting a division ratio of 16, the RX

LO can be set to 140 MHz (see the Programming the TRF2443 Synthesizers section).

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TRF2443IPFPR Datasheet(PDF) 54 Page - Texas Instruments

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