TRF2443IPFPR datasheet(61/72 Pages) TI

61 / 72 page

Power UP

POWER ALERT STATE

PWRDET = LOW

V1 = X

V1 = ?

SW_RESET = 0

V1 = HIGH

NORMAL MODE

PWRDET = HIGH

V1 = LOW

PRE-ALARM MODE

PWRDET = HIGH

TIME COUNTER STARTS

V1 = HIGH

COUNTER ?

V1 ?

TIME COUNTER >= td

V1 = HIGH

TIME COUNTER < td

V1 = LOW

TRF2443

www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009

The power-alarm logic includes a time counter which is used to measure how long the IQ modulator output

power stays below the user-specified threshold level. The counter is enabled when the comparator output (V1) is

HIGH and the PWRDET pin is HIGH, but it is reset to 0 when the comparator output is LOW. If the time counter

reaches the target count and V1 is still HIGH (that is, the IQ modulator output power is still low), then the logic

goes in power-alert mode and PWRDET pin goes LOW. The power-alarm logic stays in the power-alert mode

until a software reset is programmed. The device recognizes a software reset as a transition from 0 to 1 of the

controlling bit DET_RESET (SPI-3, register 1, B<20>). Figure 107 illustrates how the power-alarm logic works

from power up of the IC.

Figure 107. TX Power-Alarm Flow Chart

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TRF2443IPFPR Datasheet(PDF) 61 Page - Texas Instruments

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