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TRF2443IPFPR Datasheet(PDF) 65 Page - Texas Instruments

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Part # TRF2443IPFPR
Description  Integrated IF Transceiver for Broadband Wireless Applications
PDF  72 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TRF2443IPFPR Datasheet(HTML) 65 Page - Texas Instruments

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TEMPERATURE SENSOR
TRF2443
www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009
Table 11. DC Offset Correction DAC Programmable Range
DCOFF_BIAS _B1
DCOFF_BIAS _B0
FULL SCALE
XPICDCOFF_BIAS _B1
XPICDCOFF_BIAS _B0
0
0
10 mV
0
1
20 mV
1
0
30 mV
1
1
40 mV
The I- and Q-channel output maximum dc-offset correction range can be calculated by multiplying the values in
Table 11 by the baseband PGA gain. The LSB of the digital correction is dependent on the programmed
maximum correction range. The dc offset correction DAC output is affected by a change in the PGA gain, but if
the initial calibration yields optimum results, then the adjustment of the PGA gain during normal operation does
not significantly impair the dc offset balance.
The dc offset correction DACs are programmed from the internal registers when the RXBB_CALSELECT bit
(SPI-3, register 7, B<21>) is set to 1 (default value at power on). At start-up, the internal registers are loaded at
half-scale, corresponding to a decimal value of 128. The autocalibration for the receiver chain is initiated by
setting the EN_BB_AUTOCAL bit (SPI-3, register 5, B<5>) to 1. When the calibration is over, this bit is
automatically reset to 0. Similarly for the XPIC, by programming EN_XPIC_AUTOCAL (SPI-3, register 5, B<18>)
to 1, the baseband dc-offset calibration starts. During calibration, the RX local oscillator must be on. At each
clock cycle during an autocalibration sequence, the internal circuitry senses the output dc offset and calculates
the new dc current for the DAC. After the 13th clock cycle, the calibration is complete and the EN_BB_AUTOCAL
(or EN_XPIC_AUTOCAL) bit is reset to 0. The dc-offset DAC state is stored in the internal registers and
maintained as long as the power supply is kept on or until a new calibration is started.
The required clock speed for the optimum calibration is determined by the internal detector behavior (integration
bandwidth, gain, sensitivity). The speed of the clock can be slowed down by selecting a clock divider ratio
DCOFF_CLK<2,0> (SPI-3, register 5, B<16,14>) and/or XDCOFF_CLK<2.0> (SPI-3, register 5, B<29,27>). The
detector has more averaging time the slower the clock; hence, it can be desirable to slow down the clock speed
for a given condition to achieve optimum results.
The internal registers controlling the internal dc current DAC for the receiver chain are accessible through the
SPI (SPI-3, register 7, B<20,5>), providing a user-programmable method for implementing the dc-offset
calibration. To employ this option, the RXBB_CALSELECT (SPI-3, register 7, B<21>) bit must be set to 0. During
this calibration, an external instrument monitors the output dc offset between the I/Q differential outputs and
programs the internal registers RXBBI_DCOFF<7,0> (SPI-3, register 7, B<12,5) and RXBBQ_DCOFF<7,0>,
(SPI-3, register 7, B<20,13) to cancel the dc offset.
The TRF2443 integrates a temperature sensor that can be used to monitor the die junction temperature. To
enable it, PWD_TEMPSENS (SPI-3, register 4, B<22>) must be set to 0. The temperature sensor generates a dc
voltage proportional to the measured temperature. This voltage is output at the TEMPOUT pin (pin 37). The
output voltage goes typically from 500 mV at –40°C to 970 mV at 150°C.
The temperature sensor output can also be read through the SPI. An internal ADC converts the analog
information to digital bits. The internal data-converter is enabled by setting PWD_TEMPADC (SPI-3, register 4,
B<21>) to 0. The conversion starts when ADC_START (SPI-3, register 4, B<5>) is set to 1. The internal ADC
uses a clock (ADC clock) generated from the external reference clock with a divide-by-16 frequency divider. At
the end of conversion, ADC_START is reset to 0 and the 8-bit word ADC output is transferred into SPI-3, register
0, B<29,22>, where it can be read through the readback mode (See the READBACK MODE section). When the
data conversion from analog to digital is complete, the CONVDONE bit (SPI-3, register 0, B<5>) is set to 1. If the
ADC input signal is outside its input voltage range, the OUTRANGE bit (SPI-3, register 0, B<6>) is 1. The ADC
input voltage range is 1 V, from 0.125 V to 1.125 V.
Copyright © 2009, Texas Instruments Incorporated
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