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TRF2443IPFPR Datasheet(PDF) 51 Page - Texas Instruments |
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TRF2443IPFPR Datasheet(HTML) 51 Page - Texas Instruments |
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51 / 72 page ![]() READBACK MODE 32nd Write clock pulse 1st Read clock pulse 2nd Read clock pulse 32nd Read clock pulse 33rd Read clock pulse “End of Write Cycle” pulse ReadBack Data Bit31 Read Back Data Bit1 Read Back Data Bit29 ReadBack Data Bit30 ReadBack Data Bit0 CLOCK READBACK DATA t d t su2 t w LATCH ENABLE 1st Write clock pulse t su1 t h t (CLK) 32nd Writes clock pulse DB2 Address Bit2 DB1 Address Bit1 CLOCK DATA t (CL) t (CH) LATCH ENABLE DB3 Address Bit3 t w t su2 t su3 DB0 (LSB) Address Bit0 DB29 DB30 DB31 (MSB) TRF2443 www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 Table 8. TX Power-Detector Response-Time Delay vs PWRDET_DEL<1,0> PWRDET_DEL DET DELAY 00 5 µs 01 10 µs 10 20 µs 11 40 µs PWRDET<2,0>: TX power-detector threshold-level control The TRF2443 implements the capability to read back the content of the serial programming-interface registers. Each readback is composed of two phases: 1. Writing a request to read back data 2. Reading the actual data of the internal registers (see timing diagram in Figure 100). During the writing phase, a command is sent to the TRF2443 to set it in readback mode and to specify which register is to be read. In the proper reading phase, at each rising clock edge, the internal data is transferred to the RDBKSPI pin and can be read at the following falling edge (LSB first). The first clock after the LE goes high (end of writing cycle) is idle, and the following 32 clock pulses transfer the internal register content to the RDBKSPI pin. Figure 100. SPI Readback Timing Diagram Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 51 Product Folder Link(s): TRF2443 |
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