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TRF2443IPFPR Datasheet(PDF) 3 Page - Texas Instruments

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Part # TRF2443IPFPR
Description  Integrated IF Transceiver for Broadband Wireless Applications
PDF  72 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TRF2443IPFPR Datasheet(HTML) 3 Page - Texas Instruments

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TRANSMITTER DESCRIPTION
6
FromSPI
0/90
Tofeedback
switch
From TX
PLL
TX_OUT
TXQ_IN
TXI_IN
Level
Detect
TX_PWD
ATT
TXAMP
V
CC
V
CC
SYNTHESIZERS DESCRIPTION
TRF2443
www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009
receiver chain is a low-noise, highly linear IF amplifier (LNA). Its input is differential and internally matched to 50
Ω. The TRF2443 LNA attenuation is programmable from 0 dB to –19 dB, corresponding to an LNA gain of 17 dB
to –2 dB (1-dB steps). The LNA is followed by three analog-controlled VGAs that provide more than 60 dB of
gain range. The IFVGA1 output and IFVGA2 input can be connected externally (pins IFOUT and IFIN) through
an external IF filter. An internal switch gives the flexibility to bypass the external filter. The VGAs provide a gain
slope of 51 dB/V. The IFVGA3 drives the demodulator, which downconverts the IF input signal directly to
baseband in-phase and quadrature. The demodulator block includes the local oscillator in-phase and quadrature
generation circuitry followed by the LO buffer. The TRF2443 baseband section integrates a programmable-gain
amplifier (PGA) and programmable low-pass filter. The baseband PGA minimum gain is 9 dB, and the maximum
gain is 33 dB. The TRF2443 baseband low-pass filter cutoff frequency can be programmed from 2 MHz to 11
MHz by setting the cutoff-frequency control bits appropriately. The baseband output buffers (ADC drivers) are
designed to drive directly an analog-to-digital converter (ADC), either dc- or ac-coupled. The output common
mode of the ADC drivers is set externally via the RXBBCM pin (pin 40). When the TRF2443 is dc-connected to
the ADC, the same dc common mode can be used for both the ADC and the TRF2443 baseband output.
Figure 3. Transmitter Chain Block Diagram
The transmitter chain integrates an IQ modulator followed by a variable attenuator and the final transmitter
amplification stage. The last two blocks provide over 35 dB of gain range. A power-alarm circuit monitors the
level at the modulator output, and its digital output goes low if the signal level falls below the user-specified
threshold level relative to the expected level. The first block of the transmitter chain is the IQ modulator, which
upconverts the incoming in-phase and quadrature signals to the TX IF frequency. The TRF2443 can be either ac-
or dc-coupled to the digital-to-analog converter (DAC). The IQ modulator drives a variable attenuator. This block
provides 5.5 dB of total attenuation range in 0.5-dB steps. The output amplifier integrates five attenuation steps
of 6 dB each for total of 30 dB. The output amplifier in combination with the variable attenuator provides over
35.5 dB of monotonic output power control (0.5-dB steps).
TRF2443 integrates two complete integer synthesizers for the receiver and transmitter chain. The RXVCO
operates at 16 times the typical RX input frequency, and the TXVCO operates at 8 times the typical TX output
frequency.
Each synthesizer is composed of:
• High-frequency VCO (around 2720 MHz for the TX VCO and 2240 MHz for the RX VCO)
• N-divider (driven by the high-frequency VCO) done by an 8/9 prescaler followed by an A-B counter that drives
the phase-frequency detector
• Phase-frequency detector (PFD) (driven by the N-divider) that compares the VCO divided by N to the
reference clock divided by R signals
• Charge pump (driven by the PFD) which creates up and down current pulses, based on the incoming signals
from the PFD. Its output is filtered and transformed to voltage by the external loop filter and applied to the
VCO input control voltage.
• An external reference clock must be applied to the REFIN (pin 16). The incoming signal is buffered and goes
through a programmable divider (R-divider).
Copyright © 2009, Texas Instruments Incorporated
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