TRF2443IPFPR datasheet(57/72 Pages) TI

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Calibrating TRF2443 TX and RX VCO

Synthesizer Lock-Detector Indicator

TRF2443

www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009

where:

N: division ratio of the N-divider

R: division ratio of the R-divider

K: multiplier factor; k = 1 for RX synthesizer; k = 2 for the TX synthesizer.

Knowing the fRef, it is possible to calculate the required N and R values to synthesize any output frequency within

the VCO frequency range.

Example

Suppose we want to synthesize the TX LO to be 340 MHz and the input reference frequency is 20 MHz.

LOTX = 340 MHz

fRef = 20 MHz

fVCO-TX = 2720 MHz (8 × LOTX)

Because fVCO-TX is an integer multiple of fRef, we can set the R divider to 1.

R = 1

N = fVCO-TX / (k × fRef) × R = 68

Then the TRF2443 SPI can be programmed as follows:

R = 1

→ TXRDIV<13,0> = <00 0000 0000 0001> (SPI-1, register 1, B<18,5>)

N = 68

→ TX_NINT<15,0> = <0000 0000 0100 0100> (SPI-1, register 2, B<20,5>)

LO divider set to 8

→ TXDIV_SEL = 1 (SPI-1, register 2, B<26>).

Both TRF2443 VCOs are based on a cross-coupled LC tank architecture. The tank is composed of a high-Q

integrated spiral inductor, a varactor, and an array of capacitors which is digitally controlled. To tune the VCO to

a certain frequency, the correct configuration for the array of capacitors is required. The capacitor array can be

configured automatically or manually.

The calibration mode is controlled by TXCAL_SEL (SPI-1, register 2, B<30>) for the TX VCO and by

RXCAL_SEL (SPI-2, register 2, B<30>) for the RX VCO. Setting these two bits to 1 selects the automatic

calibration mode. The calibration starts when EN_TXCAL (SPI-1, register 2, B<31>) and/or EN_RXCAL (SPI-2,

clock through a frequency divider, whose division ratio can be programmed with TXCAL_CLK<2,0> (SPI-1,

TXCAL_CLK<2,0> and RXCAL_CLK<2,0> = <101>, which corresponds to a divider value of 1024 and a clock

speed of 20 MHz.

The manual-mode calibration, used mainly for debugging purposes, is activated by setting TXCAL_SEL (SPI-1,

controlled by TXVCO_TRIM<5,0> (SPI-1, register 4, B<31,26>) for the TX VCO and RXVCO_TRIM<6,0> (SPI-2,

The TRF2443 integrates a PLL lock-detector circuit. When both the TX and RX synthesizers are locked,

LOCKDET (pin 5) goes high. The settling time of the lock-detector circuitry can be set externally by sizing the

capacitor placed between LDCAP (pin 38) and ground. The size of capacitor on this pin sets the time constant

Tld of the lock detect circuit. If either the TX PLL or the RX PLL lock-detect circuit indicates a loss of lock, the

LOCKDET pin goes low immediately.

If the lock-detect circuits of the TX and the RX PLLs have not indicated a loss of lock for a time > Tld, the

LOCKDET pin goes high. For a 20-MHz PFD frequency, a 1-nF capacitor is suggested, corresponding to a 10-

µs

deglitch time.

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