TRF2443IPFPR datasheet(53/72 Pages) TI

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TRF2443

www.ti.com ................................................................................................................................... SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009

Table 10. SPI Register Banks Readback Setup

SUGGESTED

BITS

NAME

DESCRIPTION

VALUE

ADDR <0>

ADDR <1>

Address bits

ADDR <2>

ADDR <3>

TX PLL (01); RX PLL (10); TX-RX SPI (11)

ADDR <4>

N/C

B10

N/C

B11

N/C

B12

N/C

B13

N/C

B14

N/C

B15

N/C

B16

N/C

B17

N/C

Data field

B19

N/C

B20

N/C

B21

N/C

B22

N/C

B23

N/C

B24

N/C

B25

N/C

B26

N/C

B27

N/C

B28

RB_REG<0>

Address of the register within the bank that is being read back;

B29

RB_REG<1>

Reg 1(001) to Reg 5(101) in TX PLL/RX PLL;

Reg 0(000) to Reg 7(111) in TX-RX SPI

B30

RB_REG<2>

B31

RB_Enable

→ Put the device in readback mode

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