TRF2443IPFPR datasheet(52/72 Pages) TI

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Readback From the Internal Register Banks

TRF2443

SLWS217A – SEPTEMBER 2009 – REVISED SEPTEMBER 2009 ................................................................................................................................... www.ti.com

Table 9. SPI Readback Timing

PARAMETER

MIN

TYP

MAX

UNITS

COMMENTS

Hold time, data to clock

tSU1

Setup time, data to clock

t(CL)

Clock low duration

t(CH)

Clock high duration

tSU2

Setup time, clock to enable

Enable time

Equals clock period

t(CLK)

Clock period

tSU3

Setup time, latch to data

Delay time, clock to readback-data output

The TX PLL (SPI-1) and RX PLL (SPI-2) register banks each contain six registers: register 0 (000) through

actual PLL control registers. In the case of the TX PLL (SPI-1) and RX PLL (SPI-2) register banks, register 0

contains no information. Therefore, it is not possible to read back register 0 from these register banks.

The TX-RX (SPI-3) register bank contains eight registers: register 0 (000) through register 7 (111). Register 0

(000) is used only for the readback operation, whereas registers 1 through 7 are the actual TX and RX control

registers. In the case of the TX-RX register bank (SPI-3), register 0 is used to store some TRF2443 internal data.

Therefore, it is possible to read back register 0 from this register bank, as it contains this data.

To read back a register from any of these register banks, register 0 of the register bank which contains the

and specifies the register to be read:

• Set B<31> to 1 to put the TRF2443 in readback mode.

• Set B<30,28> equal to the address of the register to be read (001 to 101 in the case of TX PLL/RX PLL; 000

to 111 in the case of TX-RX SPI).

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