82G33 datasheet(130/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

130

Datasheet

5.2.1

CHDECMISC—Channel Decode Miscellaneous

B/D/F/Type:

0/0/0/MCHBAR

Address Offset:

111h

Default Value:

00h

Access:

RW/L

Size:

8 bits

This register has Miscellaneous CHDEC/MAGEN configuration bits.

Bit

Access &

Default

Description

RW/L

Reserved

6:5

RW/L

00b

Enhanced Mode Select (ENHMODESEL):

00 = Swap Enabled for Bank Selects and Rank Selects

01 = XOR Enabled for Bank Selects and Rank Selects

10 = Swap Enabled for Bank Selects only

11 = XOR Enabled for Bank Select only

This register is locked by ME stolen Memory lock.

RW/L

Ch2 Enhanced Mode (CH2_ENHMODE): This bit enables Enhanced

addressing mode of operation is enabled for Ch 2.

0 = Disable

1 = Enable

RW/L

Ch1 Enhanced Mode (CH1_ENHMODE): This bit enables Enhanced

addressing mode of operation is enabled for Ch 1.

0 = Disable

1 = Enable

RW/L

Ch0 Enhanced Mode (CH0_ENHMODE): This bit enables Enhanced

addressing mode of operation is enabled for Ch 0.

0 = Disable

1 = Enable

RW/L

Reserved

RW/L

EP Present (EPPRSNT): This bit indicates whether EP UMA is

present in the system or not.

0 = Not Present

1 = Present

This register is locked by ME stolen Memory lock.

82G33 Datasheet(PDF) 130 Page - Intel Corporation

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