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82G33 Datasheet(PDF) 133 Page - Intel Corporation

Part # 82G33
Description  Graphics and Memory Controller Hub
PDF  437 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82G33 Datasheet(HTML) 133 Page - Intel Corporation

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DRAM Controller Registers (D0:F0)
Datasheet
133
5.2.4
C0DRB2—Channel 0 DRAM Rank Boundary Address 2
B/D/F/Type:
0/0/0/MCHBAR
Address Offset:
204–205h
Default Value:
0000h
Access:
RO, R/W
Size:
16 bits
See C0DRB0 register for programming information.
Bit
Access &
Default
Description
15:10
RO
000000b
Reserved
9:0
R/W
000h
Channel 0 DRAM Rank Boundary Address 2 (C0DRBA2): This
register defines the DRAM rank boundary for rank2 of Channel 0 (64
MB granularity)
= (R2 + R1 + R0)
R0 = Total Rank 0 memory size is 64 MB
R1 = Total Rank 1 memory size is 64 MB
R2 = Total Rank 2 memory size is 64 MB
R3 = Total Rank 3 memory size is 64 MB
5.2.5
C0DRB3—Channel 0 DRAM Rank Boundary Address 3
B/D/F/Type:
0/0/0/MCHBAR
Address Offset:
206–207h
Default Value:
0000h
Access:
R/W, RO
Size:
16 bits
See C0DRB0 register for programming information.
Bit
Access &
Default
Description
15:10
RO
000000b
Reserved
9:0
R/W
000h
Channel 0 DRAM Rank Boundary Address 3 (C0DRBA3): This
register defines the DRAM rank boundary for rank3 of Channel 0 (64
MB granularity)
= (R3 + R2 + R1 + R0)
R0 = Total Rank 0 memory size is 64 MB
R1 = Total Rank 1 memory size is 64 MB
R2 = Total Rank 2 memory size is 64 MB
R3 = Total Rank 3 memory size is 64 MB



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