82G33 datasheet(134/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

134

Datasheet

5.2.6

C0DRA01—Channel 0 DRAM Rank 0,1 Attribute

B/D/F/Type:

0/0/0/MCHBAR

Address Offset:

208–209h

Default Value:

0000h

Access:

R/W

Size:

16 bits

The DRAM Rank Attribute Registers define the page sizes/number of banks to be used

when accessing different ranks. These registers should be left with their default value

(all zeros) for any rank that is unpopulated, as determined by the corresponding

CxDRB registers. Each byte of information in the CxDRA registers describes the page

size of a pair of ranks. Channel and rank map:

Ch 0, Rank 0, 1= 208h–209h

Ch 0, Rank 2, 3 = 20Ah–20Bh

Ch 1, Rank 0, 1= 608h–609h

Ch 1, Rank 2, 3= 60Ah–60Bh

DRA[7:0] = "00" means Cfg 0 , DRA[7:0] ="01" means Cfg 1 .... DRA[7:0] = "09" means Cfg 9

and so on.

Table 5-3. DRAM Rank Attribute Register Programming

Tech

DDRx

Depth

Width

Row

Col

Bank

Row

Size

Page

Size

512Mb

64M

512 MB

512Mb

32M

256 MB

512Mb

64M

512 MB

512Mb

32M

256 MB

1 Gb

2,3

128M

1 GB

1 Gb

2,3

64M

512 MB

NOTE:

DDR3 is only supported on the 82G33 GMCH and 82P35 MCH components.

Bit

Access &

Default

Description

15:8

R/W

00h

Channel 0 DRAM Rank-1 Attributes (C0DRA1): This field defines

DRAM pagesize/number-of-banks for rank1 for given channel. See

Table 5-3 for programming.

7:0

R/W

00h

Channel 0 DRAM Rank-0 Attributes (C0DRA0): This field defines

DRAM page size/number-of-banks for rank0 for given channel. See

Table 5-3 for programming.

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