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82G33 Datasheet(PDF) 138 Page - Intel Corporation

Part # 82G33
Description  Graphics and Memory Controller Hub
PDF  437 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82G33 Datasheet(HTML) 138 Page - Intel Corporation

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DRAM Controller Registers (D0:F0)
138
Datasheet
5.2.11
C0CYCTRKRD—Channel 0 CYCTRK READ
B/D/F/Type:
0/0/0/MCHBAR
Address Offset:
258–25Ah
Default Value:
000000h
Access:
RW, RO
Size:
24 bits
This register provides Channel 0 CYCTRK RD.
Bit
Access &
Default
Description
23:21
RO
000b
Reserved
20:17
RW
0h
Min ACT To READ Delay (C0sd_cr_act_rd): This field indicates the
minimum allowed spacing (in DRAM clocks) between the ACT and
READ commands to the same rank-bank. This field corresponds to
tRCD_rd in the DDR Specification.
16:12
RW
00000b
Same Rank Write To READ Delay (C0sd_cr_wrsr_rd): This field
indicates the minimum allowed spacing (in DRAM clocks) between the
WRITE and READ commands to the same rank. This field corresponds
to tWTR in the DDR Specification.
11:8
RW
0000b
Different Ranks Write To READ Delay (C0sd_cr_wrdr_rd): This
field indicates the minimum allowed spacing (in DRAM clocks) between
the WRITE and READ commands to different ranks. This field
corresponds to tWR_RD in the DDR Specification.
7:4
RW
0000b
Same Rank Read To Read Delay (C0sd_cr_rdsr_rd): This field
indicates the minimum allowed spacing (in DRAM clocks) between two
READ commands to the same rank.
3:0
RW
0000b
Different Ranks Read To Read Delay (C0sd_cr_rddr_rd): This
field indicates the minimum allowed spacing (in DRAM clocks) between
two READ commands to different ranks. This field corresponds to
tRD_RD.
5.2.12
C0CYCTRKREFR—Channel 0 CYCTRK REFR
B/D/F/Type:
0/0/0/MCHBAR
Address Offset:
25B–25Ch
Default Value:
0000h
Access:
RO, RW
Size:
16 bits
This register provides Channel 0 CYCTRK Refresh.
Bit
Access &
Default
Description
15:13
RO
000b
Reserved
12:9
RW
0000b
Same Rank PALL to REF Delay (C0sd_cr_pchgall_rfsh): This
field indicates the minimum allowed spacing (in DRAM clocks)
between the PRE-ALL and REF commands to the same rank.
8:0
RW
000000000b
Same Rank REF to REF Delay (C0sd_cr_rfsh_rfsh): This field
indicates the minimum allowed spacing (in DRAM clocks) between
two REF commands to same ranks.



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