 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
82G33 Datasheet(PDF) 142 Page - Intel Corporation |
|
|
|||||||||||||||||||||||||||||
82G33 Datasheet(HTML) 142 Page - Intel Corporation |
|
|
142 / 437 page  DRAM Controller Registers (D0:F0) 142 Datasheet Bit Access & Default Description 15:14 RW 00b DRAM Refresh Low Watermark (REFLOWWM): When the refresh count exceeds this level, a refresh request is launched to the scheduler and the dref_low flag is set. 00 = 1 01 = 2 10 = 3 11 = 4 13:0 RW 001100001 10000b Refresh Counter Time Out Value (REFTIMEOUT): Program this field with a value that will provide 7.8 us at the memory clock frequency. At various memory clock frequencies this results in the following values: 667 MHz -> 1450 hex 5.2.15 C0ODTCTRL—Channel 0 ODT Control B/D/F/Type: 0/0/0/MCHBAR Address Offset: 29C–29Fh Default Value: 00000000h Access: RO, RW Size: 32 bits This register provides ODT controls. Bit Access & Default Description 31:12 RO 00000h Reserved 11:8 RW 0000b Reserved 7:4 RW 0000b Reserved 3:0 RW 0000b Reserved |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
