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82G33 Datasheet(PDF) 145 Page - Intel Corporation |
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82G33 Datasheet(HTML) 145 Page - Intel Corporation |
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145 / 437 page ![]() DRAM Controller Registers (D0:F0) Datasheet 145 5.2.20 C1DRA01—Channel 1 DRAM Rank 0,1 Attributes B/D/F/Type: 0/0/0/MCHBAR Address Offset: 608–609h Default Value: 0000h Access: RW/L Size: 16 bits The operation of this register is detailed in the description for register C0DRA01. Bit Access & Default Description 15:8 RW/L 00h Channel 1 DRAM Rank-1 Attributes (C1DRA1): See C0DRA1 register. This register is locked by ME stolen Memory lock. 7:0 RW/L 00h Channel 1 DRAM Rank-0 Attributes (C1DRA0): See C0DRA0 register. This register is locked by ME stolen Memory lock. 5.2.21 C1DRA23—Channel 1 DRAM Rank 2,3 Attributes B/D/F/Type: 0/0/0/MCHBAR Address Offset: 60A–60Bh Default Value: 0000h Access: RW/L Size: 16 bits The operation of this register is detailed in the description for register C0DRA01. Bit Access & Default Description 15:8 RW/L 00h Channel 1 DRAM Rank-3 Attributes (C1DRA3): See C0DRA3 register. This register is locked by ME stolen Memory lock. 7:0 RW/L 00h Channel 1 DRAM Rank-2 Attributes (C1DRA2): See C0DRA2 register. This register is locked by ME stolen Memory lock. |
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