82G33 datasheet(143/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

Datasheet

143

5.2.16

C1DRB0—Channel 1 DRAM Rank Boundary Address 0

B/D/F/Type:

0/0/0/MCHBAR

Address Offset:

600–601h

Default Value:

0000h

Access:

RW/L, RO

Size:

16 bits

The operation of this register is detailed in the description for register C0DRB0.

Bit

Access &

Default

Description

15:10

000000b

Reserved

9:0

RW/L

000h

Channel 1 DRAM Rank Boundary Address 0 (C1DRBA0): See

C0DRB0 register. In stacked mode, if this is the topmost populated

rank in Channel 1, program this value to be cumulative of Ch0

DRB3.

This register is locked by ME stolen Memory lock.

5.2.17

C1DRB1—Channel 1 DRAM Rank Boundary Address 1

B/D/F/Type:

0/0/0/MCHBAR

Address Offset:

602–603h

Default Value:

0000h

Access:

RW/L, RO

Size:

16 bits

The operation of this register is detailed in the description for register C0DRB0.

Bit

Access &

Default

Description

15:10

000000b

Reserved

9:0

RW/L

000h

Channel 1 DRAM Rank Boundary Address 1 (C1DRBA1): See

C0DRB1 register. In stacked mode, if this is the topmost populated

rank in Channel 1, program this value to be cumulative of Ch0 DRB3.

This register is locked by ME stolen Memory lock.

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