82G33 datasheet(144/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

144

Datasheet

5.2.18

C1DRB2—Channel 1 DRAM Rank Boundary Address 2

B/D/F/Type:

0/0/0/MCHBAR

Address Offset:

604–605h

Default Value:

0000h

Access:

RW/L, RO

Size:

16 bits

The operation of this register is detailed in the description for register C0DRB0.

Bit

Access &

Default

Description

15:10

000000b

Reserved

9:0

RW/L

000h

Channel 1 DRAM Rank Boundary Address 2 (C1DRBA2): See

C0DRB2 register. In stacked mode, if this is the topmost populated

rank in Channel 1, program this value to be cumulative of Ch0 DRB3.

This register is locked by ME stolen Memory lock.

5.2.19

C1DRB3—Channel 1 DRAM Rank Boundary Address 3

B/D/F/Type:

0/0/0/MCHBAR

Address Offset:

606–607h

Default Value:

0000h

Access:

RW/L, RO

Size:

16 bits

The operation of this register is detailed in the description for register C0DRB0.

Bit

Access &

Default

Description

15:10

000000b

Reserved

9:0

RW/L

000h

Channel 1 DRAM Rank Boundary Address 3 (C1DRBA3): See

C0DRB3 register. In stacked mode, this will be cumulative of Ch0

DRB3.

This register is locked by ME stolen Memory lock.

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