 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
82G33 Datasheet(PDF) 146 Page - Intel Corporation |
|
|
|||||||||||||||||||||||||||||
82G33 Datasheet(HTML) 146 Page - Intel Corporation |
|
|
146 / 437 page  DRAM Controller Registers (D0:F0) 146 Datasheet 5.2.22 C1CYCTRKPCHG—Channel 1 CYCTRK PCHG B/D/F/Type: 0/0/0/MCHBAR Address Offset: 650–651h Default Value: 0000h Access: RO, RW Size: 16 bits This register provides Channel 1 CYCTRK Precharge. Bit Access & Default Description 15:11 RO 00000b Reserved 10:6 RW 00000b Write To PRE Delayed (C1sd_cr_wr_pchg): This field indicates the minimum allowed spacing (in DRAM clocks) between the WRITE and PRE commands to the same rank-bank. This field corresponds to tWR in the DDR Specification. 5:2 RW 0000b READ To PRE Delayed (C1sd_cr_rd_pchg): This field indicates the minimum allowed spacing (in DRAM clocks) between the READ and PRE commands to the same rank-bank 1:0 RW 00b PRE To PRE Delayed (C1sd_cr_pchg_pchg): This field indicates the minimum allowed spacing (in DRAM clocks) between two PRE commands to the same rank. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
