82G33 datasheet(150/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

150

Datasheet

5.2.26

C1CKECTRL—Channel 1 CKE Control

B/D/F/Type:

0/0/0/MCHBAR

Address Offset:

660–663h

Default Value:

00000800h

Access:

RW/L, RW, RO

Size:

32 bits

This register provides Channel 1 CKE Controls.

Bit

Access &

Default

Description

31:28

Reserved

start the self-refresh exit sequence (sd1_cr_srcstart): This

field indicates the request to start the self-refresh exit sequence.

26:24

000b

CKE pulse width requirement in high phase

(sd1_cr_cke_pw_hl_safe): This field indicates CKE pulse width

requirement in high phase. This field corresponds to tCKE (high) in

the DDR Specification.

RW/L

Rank 3 Population (sd1_cr_rankpop3):

1 = Rank 3 populated

0 = Rank 3 not populated.

This register is locked by ME stolen Memory lock

RW/L

Rank 2 Population (sd1_cr_rankpop2):

1 = Rank 2 populated

0 = Rank 2 not populated

This register is locked by ME stolen Memory lock.

RW/L

Rank 1 Population (sd1_cr_rankpop1):

1 = Rank 1 populated

0 = Rank 1 not populated.

This register is locked by ME stolen Memory lock.

RW/L

Rank 0 Population (sd1_cr_rankpop0):

1 = Rank 0 populated

0 = Rank 0 not populated

This register is locked by ME stolen Memory lock.

19:17

000b

CKE pulse width requirement in low phase

(sd1_cr_cke_pw_lh_safe): This configuration register indicates

CKE pulse width requirement in low phase. This field corresponds

to tCKE (low) in the DDR Specification.

Enable CKE toggle for PDN entry/exit (sd1_cr_pdn_enable):

This configuration bit indicates that the toggling of CKEs (for PDN

entry/exit) is enabled.

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