82G33 datasheet(153/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

Datasheet

153

Bit

Access &

Default

Description

15:14

00b

DRAM Refresh Low Watermark (REFLOWWM): When the refresh

count exceeds this level, a refresh request is launched to the scheduler

and the dref_low flag is set.

00 = 1

01 = 2

10 = 3

11 = 4

13:0

00110000

110000b

Refresh Counter Time Out Value (REFTIMEOUT): Program this

field with a value that will provide 7.8 us at the memory clock

frequency. At various memory clock frequencies this results in the

following values:

266 MHz -> 820 hex

333 MHz -> A28 hex

400 MHz -> C30 hex

533 MHz -> 104B hex

666 MHz -> 1450 hex

5.2.28

C1ODTCTRL—Channel 1 ODT Control

B/D/F/Type:

0/0/0/MCHBAR

Address Offset:

69C–69Fh

Default Value:

00000000h

Access:

RO, RW

Size:

32 bits

This register provides ODT controls.

Bit

Access &

Default

Description

31:12

00000h

Reserved

11:8

DRAM ODT for Read Commands (sd1_cr_odt_duration_rd):

Specifies the duration in MDCLKs to assert DRAM ODT for Read

Commands. The Async value should be used when the Dynamic

Powerdown bit is set. Else use the Sync value.

7:4

DRAM ODT for Write Commands (sd1_cr_odt_duration_wr):

Specifies the duration in MDCLKs to assert DRAM ODT for Write

Commands. The Async value should be used when the Dynamic

Powerdown bit is set. Else use the Sync value.

3:0

MCH ODT for Read Commands (sd1_cr_mchodt_duration):

Specifies the duration in MDCLKs to assert MCH ODT for Read

Commands

82G33 Datasheet(PDF) 153 Page - Intel Corporation

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