82G33 datasheet(157/437 Pages) INTEL

157 / 437 page

DRAM Controller Registers (D0:F0)

Datasheet

157

5.2.36

EPDCYCTRKWRTACT—EPD CYCTRK WRT ACT

B/D/F/Type:

0/0/0/MCHBAR

Address Offset:

A1C–A1Fh

Default Value:

00000000h

Access:

RO, RW

Size:

32 bits

This register provides EPD CYCTRK WRT ACT Status.

Bit

Access &

Default

Description

31:21

000h

Reserved

20:17

0000b

ACT to ACT Delayed (C0sd_cr_act_act[): This field indicates the

minimum allowed spacing (in DRAM clocks) between two ACT

commands to the same rank.

16:13

0000b

PRE to ACT Delayed (C0sd_cr_pre_act): This field indicates the

minimum allowed spacing (in DRAM clocks) between the PRE and ACT

commands to the same rank-bank:12:9R/W0000bPRE-ALL to ACT

Delayed (C0sd_cr_preall_act):

This field indicates the minimum allowed spacing (in DRAM clocks)

between the PRE-ALL and ACT commands to the same rank.

12:9

Reserved

8:0

00000000

REF to ACT Delayed (C0sd_cr_rfsh_act): This field indicates the

minimum allowed spacing (in DRAM clocks) between REF and ACT

commands to the same rank.

82G33 Datasheet(PDF) 157 Page - Intel Corporation

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