82G33 datasheet(160/437 Pages) INTEL

160 / 437 page

DRAM Controller Registers (D0:F0)

160

Datasheet

5.2.39

EPDCKECONFIGREG—EPD CKE Related Configuration

B/D/F/Type:

0/0/0/MCHBAR

Address Offset:

A28–A2Ch

Default Value:

00E0000000h

Access:

Size:

40 bits

BIOS Optimal Default

This register provides CKE related configuration for EPD.

Bit

Access &

Default

Description

39:35

00000b

EPDunit TXPDLL Count (EPDTXPDLL): This field specifies the

delay from precharge power down exit to a command that requires the

DRAM DLL to be operational. The commands are read/write.

34:32

000b

EPDunit TXP count (EPDCKETXP): This field specifies the timing

requirement for Active power down exit or fast exit pre-charge power

down exit to any command or slow exit pre-charge power down to

Non-DLL (rd/wr/odt) command.

31:29

111b

Mode Select (sd0_cr_sms): This field indicates the mode in which

the controller is operating in.

111 = Indicates normal mode of operation, else special mode of

operation.

28:27

00b

EPDunit EMRS command select. (EPDEMRSSEL): EMRS mode to

select BANK address.

01 = EMRS

10 = EMRS2

11 = EMRS3

26:24

000b

CKE pulse width requirement in high phase

(sd0_cr_cke_pw_hl_safe): This field indicates CKE pulse width

requirement in high phase.

23:20

one-hot active rank population (ep_scr_actrank): This field

indicates the active rank in a one hot manner

19:17

000b

CKE pulse width requirement in low phase

(sd0_cr_cke_pw_lh_safe): This field indicates CKE pulse width

requirement in low phase.

16:15

Reserved

EPDunit MPR mode (EPDMPR): MPR Read Mode

1 = MPR mode

0 = Normal mode

In MPR mode, only read cycles must be issued by Firmware. Page

Results are ignored by DCS and just issues the read chip select.

82G33 Datasheet(PDF) 160 Page - Intel Corporation

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