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82G33 Datasheet(PDF) 158 Page - Intel Corporation |
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82G33 Datasheet(HTML) 158 Page - Intel Corporation |
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158 / 437 page  DRAM Controller Registers (D0:F0) 158 Datasheet 5.2.37 EPDCYCTRKWRTWR—EPD CYCTRK WRT WR B/D/F/Type: 0/0/0/MCHBAR Address Offset: A20–A21h Default Value: 0000h Access: RW, RO Size: 16 bits This register provides EPD CYCTRK WRT WR Status. Bit Access & Default Description 15:12 RW 0h ACT To Write Delay (C0sd_cr_act_wr): This configuration register indicates the minimum allowed spacing (in DRAM clocks) between the ACT and WRITE commands to the same rank-bank. 11:8 RW 0h Same Rank Write To Write Delayed (C0sd_cr_wrsr_wr): This configuration register indicates the minimum allowed spacing (in DRAM clocks) between two WRITE commands to the same rank. 7:4 RO 0h Reserved 3:0 RW 0h Same Rank WRITE to READ Delay (C0sd_cr_rd_wr): This configuration register indicates the minimum allowed spacing (in DRAM clocks) between the WRITE and READ commands to the same rank |
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