82G33 datasheet(156/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

156

Datasheet

5.2.34

EPC0DRA23—EP Channel 0 DRAM Rank 2,3 Attribute

B/D/F/Type:

0/0/0/MCHBAR

Address Offset:

A0A–A0Bh

Default Value:

0000h

Access:

Size:

16 bits

See C0DRA01 register.

Bit

Access &

Default

Description

15:8

00h

Channel 0 DRAM Rank-3 Attributes (C0DRA3): This field defines

DRAM pagesize/number-of-banks for rank3 for given channel.

7:0

00h

Channel 0 DRAM Rank-2 Attributes (C0DRA2): This field defines

DRAM pagesize/number-of-banks for rank2 for given channel.

5.2.35

EPDCYCTRKWRTPRE—EPD CYCTRK WRT PRE

B/D/F/Type:

0/0/0/MCHBAR

Address Offset:

A19–A1Ah

Default Value:

0000h

Access:

RW, RO

Size:

16 bits

This register provides EPD CYCTRK WRT PRE Status.

Bit

Access &

Default

Description

15:11

00000b

ACTTo PRE Delayed (C0sd_cr_act_pchg): This field indicates the

minimum allowed spacing (in DRAM clocks) between the ACT and PRE

commands to the same rank-bank

10:6

00000b

Write To PRE Delayed (C0sd_cr_wr_pchg): This field indicates the

minimum allowed spacing (in DRAM clocks) between the WRITE and

PRE commands to the same rank-bank

5:2

0000b

READ To PRE Delayed (C0sd_cr_rd_pchg): This field indicates the

minimum allowed spacing (in DRAM clocks) between the READ and

PRE commands to the same rank-bank

1:0

00b

Reserved

82G33 Datasheet(PDF) 156 Page - Intel Corporation

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