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82G33 Datasheet(PDF) 154 Page - Intel Corporation |
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82G33 Datasheet(HTML) 154 Page - Intel Corporation |
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154 / 437 page ![]() DRAM Controller Registers (D0:F0) 154 Datasheet 5.2.29 EPC0DRB0—ME Channel 0 DRAM Rank Boundary Address 0 B/D/F/Type: 0/0/0/MCHBAR Address Offset: A00–A01h Default Value: 0000h Access: R/W, RO Size: 16 bits Bit Access & Default Description 15:10 RO 000000b Reserved 9:0 R/W 000h Channel 0 Dram Rank Boundary Address 0 (C0DRBA0): 5.2.30 EPC0DRB1—EP Channel 0 DRAM Rank Boundary Address 1 B/D/F/Type: 0/0/0/MCHBAR Address Offset: A02–A03h Default Value: 0000h Access: RO, RW Size: 16 bits See C0DRB0 register. Bit Access & Default Description 15:10 RO 000000b Reserved 9:0 RW 000h Channel 0 Dram Rank Boundary Address 1 (C0DRBA1): 5.2.31 EPC0DRB2—EP Channel 0 DRAM Rank Boundary Address 2 B/D/F/Type: 0/0/0/MCHBAR Address Offset: A04–A05h Default Value: 0000h Access: RO, RW Size: 16 bits See C0DRB0 register. Bit Access & Default Description 15:10 RO 000000b Reserved 9:0 RW 000h Channel 0 DRAM Rank Boundary Address 2 (C0DRBA2): |
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