82G33 datasheet(151/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

Datasheet

151

Bit

Access &

Default

Description

15:14

00b

Reserved

13:10

0010b

Minimum Powerdown Exit to Non-Read command spacing

(sd1_cr_txp): This configuration register indicates the minimum

number of clocks to wait following assertion of CKE before issuing a

non-read command.

1010–1111 = Reserved.

0010–1001 = 2-9 clocks

0000–0001 = Reserved.

9:1

000000000b

Self refresh exit count (sd1_cr_slfrfsh_exit_cnt): This

configuration register indicates the Self refresh exit count.

(Program to 255). This field corresponds to tXSNR/tXSRD in the DDR

Specification.

indicates only 1 DIMM populated (sd1_cr_singledimmpop):

This bit, when set, indicates that only 1 DIMM is populated.

5.2.27

C1REFRCTRL—Channel 1 DRAM Refresh Control

B/D/F/Type:

0/0/0/MCHBAR

Address Offset:

669–66Eh

Default Value:

021830000C30h

Access:

RW, RO

Size:

48 bits

This register provides settings to configure the DRAM refresh controller.

Bit

Access &

Default

Description

47:42

00h

Reserved

41:37

10000b

Direct Rcomp Quiet Window (DIRQUIET): This configuration

setting indicates the amount of refresh_tick events to wait before the

service of rcomp request in non-default mode of independent rank

refresh.

36:32

11000b

Indirect Rcomp Quiet Window (INDIRQUIET): This configuration

setting indicates the amount of refresh_tick events to wait before the

service of rcomp request in non-default mode of independent rank

refresh.

31:27

00110b

Rcomp Wait (RCOMPWAIT): This configuration setting indicates the

amount of refresh_tick events to wait before the service of rcomp

request in non-default mode of independent rank refresh.

ZQCAL Enable (ZQCALEN): This bit enables the DRAM controller to

issue ZQCAL S command periodically.

0 = Disable

1 = Enable

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