82G33 datasheet(149/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

Datasheet

149

5.2.25

C1CYCTRKRD—Channel 1 CYCTRK READ

B/D/F/Type:

0/0/0/MCHBAR

Address Offset:

658–65Ah

Default Value:

000000h

Access:

RO, RW

Size:

24 bits

This is the Channel 1 CYCTRK READ register.

Bit

Access &

Default

Description

23:21

Reserved

20:17

Min ACT To READ Delayed (C1sd_cr_act_rd): This field indicates

the minimum allowed spacing (in DRAM clocks) between the ACT and

READ commands to the same rank-bank. This field corresponds to

tRCD_rd in the DDR Specification.

16:12

00000b

Same Rank Write To READ Delayed (C1sd_cr_wrsr_rd): This

field indicates the minimum allowed spacing (in DRAM clocks) between

the WRITE and READ commands to the same rank. This field

corresponds to tWTR in the DDR Specification.

11:8

0000b

Different Ranks Write To READ Delayed (C1sd_cr_wrdr_rd):

This field indicates the minimum allowed spacing (in DRAM clocks)

between the WRITE and READ commands to different ranks. This field

corresponds to tWR_RD in the DDR Specification.

7:4

0000b

Same Rank Read To Read Delayed (C1sd_cr_rdsr_rd): This field

indicates the minimum allowed spacing (in DRAM clocks) between two

READ commands to the same rank.

3:0

0000b

Different Ranks Read To Read Delayed (C1sd_cr_rddr_rd): This

configuration register indicates the minimum allowed spacing (in

DRAM clocks) between two READ commands to different ranks. This

field corresponds to tRD_RD.

82G33 Datasheet(PDF) 149 Page - Intel Corporation

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