82G33 datasheet(159/437 Pages) INTEL

159 / 437 page

DRAM Controller Registers (D0:F0)

Datasheet

159

5.2.38

EPDCYCTRKWRTRD—EPD CYCTRK WRT READ

B/D/F/Type:

0/0/0/MCHBAR

Address Offset:

A24–A26h

Default Value:

000000h

Access:

Size:

24 bits

BIOS Optimal Default

000h

This register provides EPD CYCTRK WRT RD Status.

Bit

Access &

Default

Description

23:23

Reserved

22:20

000b

EPDunit DQS Slave DLL Enable to Read Safe (EPDSDLL2RD):

This field provides the setting for Read command safe from the point

of enabling the slave DLLs.

19:18

Reserved

17:14

Min ACT To READ Delayed (C0sd_cr_act_rd): This field indicates

the minimum allowed spacing (in DRAM clocks) between the ACT and

READ commands to the same rank-bank.

13:9

00000b

Same Rank READ to WRITE Delayed (C0sd_cr_wrsr_rd): This

field indicates the minimum allowed spacing (in DRAM clocks) between

the READ and WRITE commands.

8:6

Reserved

5:3

000b

Same Rank Read To Read Delayed (C0sd_cr_rdsr_rd): This field

indicates the minimum allowed spacing (in DRAM clocks) between two

READ commands to the same rank.

2:0

Reserved

82G33 Datasheet(PDF) 159 Page - Intel Corporation

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