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82G33 Datasheet(PDF) 162 Page - Intel Corporation |
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82G33 Datasheet(HTML) 162 Page - Intel Corporation |
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162 / 437 page  DRAM Controller Registers (D0:F0) 162 Datasheet 5.2.40 MEMEMSPACE—ME Memory Space Configuration B/D/F/Type: 0/0/0/MCHBAR Address Offset: A2Eh Default Value: 00h Access: R/W, RO Size: 8 bits This register provides settings to enable the ME memory space and define the size of EP memory if enabled. Bit Access & Default Description 7:5 RO 000b Reserved 4:0 R/W 00000b ME-UMA(Sx) Region Size (EXRS): These bits are written by firmware to indicate the desired size of ME-UMA(Sx) memory region. This is done prior to bring up core power and allowing BIOS to initialize memory. Within channel 0 DDR, the physical base address for MEUMA(Sx) will be determined by: ME-UMA(Sx)BASE = C0DRB3 - EXRS This forces the ME-UMA(Sx) region to always be positioned at the top of the memory populated in channel 0. The approved sizes for ME- UMA(Sx) are values between 0000b (0MB, no ME-UMA(Sx) region) and 10000b (16MB ME-UMA(Sx) region) |
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